The present application relates to semiconductor technology and more particularly to a method and structure to enable tensily strained silicon nanowires within an nFET device region, and compressively stained silicon germanium alloy (SiGe) nanowires in a pFET device region.
For more than three decades, the continued miniaturization of metal oxide semiconductor field effect transistors (MOSFETs) has driven the worldwide semiconductor industry. Various showstoppers to continue scaling have been predicated for decades, but a history of innovation has sustained Moore's Law in spite of many challenges. However, there are growing signs today that MOSFETs are beginning to reach their traditional scaling limits. Since it has become increasingly difficult to improve MOSFETs and therefore complementary metal oxide semiconductor (CMOS) performance through continued scaling, further methods for improving performance in addition to scaling have become critical.
The use of non-planar semiconductor devices such as, for example, semiconductor nanowire field effect transistors (FETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Semiconductor nanowire FETs can achieve higher drive currents with increasingly smaller dimensions as compared to conventional planar FETs.
For semiconductor nanowire device performance increase, a strained channel material is needed. For CMOS devices, tensile strained silicon nanowires are beneficial for nFET devices, but not for pFET devices. In current nanowire technology, all the nanowire structures consists of unstrained semiconductor materials or only one strained semiconductor material, either nFET or pFET. A need thus exist for providing stained CMOS nanowires with both strained nFET nanowires and strained pFET nanowires on a same substrate.